As it is known, level shifter circuits (or level shifters) have several applications, for example, wherever it is required to interface two circuit stages operating at different voltage levels. In particular, level shifter circuits are used in non-volatile memory devices, for example, of a flash or PCM (Phase-Change Memory) type, of an embedded type (the so-called eNVMs—embedded Non-Volatile Memories). In these memory devices an internal supply voltage is present (the so-called logic supply voltage Vdd, with low voltage values, for example, comprised between 1 V and 1.35 V). Moreover, in order to be able to modify (during programming or erasing) and read the contents of the memory cells, use of higher operating voltages, with high voltage values, for example, higher than or equal to 3.6 V, is required.
Due to the different range of values of the voltages present in these memory devices, use of level shifter circuits is thus required, in order to interface and put in communication low-voltage and high-voltage circuit stages.
Level shifter circuits of a known type are generally made with high-voltage (HV) transistors, i.e., ones that are able to operate with high voltage values without undergoing failure (for example, of the corresponding junction oxides), or else, in some cases, with mixed solutions of high-voltage transistors and low-voltage (LV) transistors, i.e., ones that are able to operate without danger of undergoing failure only for voltage values not higher than a given threshold voltage, typically in the region of the logic supply voltage Vdd.
In a known way, HV transistors have structural characteristics, as compared to LV transistors, for example, as regards a greater thickness of the gate oxide, that make it possible to withstand without undergoing failure higher voltage values between their corresponding control and current-conduction terminals.
FIG. 1 shows a level shifter circuit of a known type, designated by 1, designed to shift an input signal Vin operating in the low-voltage range [0, Vdd] into an output signal Vout operating in the high-voltage range [0, VHV], where VHV is a high, or level-shifted, voltage, in what follows referred to as “high voltage”, of an appropriate value, greater than the logic supply voltage Vdd.
The level shifter circuit 1 comprises: a first input transistor 2, of an LV NMOS type (for example, having a first thickness of the gate oxide such as to undergo failure for high voltage values), connected between a first reference terminal (set at ground, gnd) and a first transfer node N1, and having the gate terminal connected to a first input terminal IN1, which receives the input signal Vin; and a second input transistor 3, which is also of an LV NMOS type, connected between the first reference terminal set at ground and a second transfer node N2, and having the gate terminal connected to a second input terminal IN2, which receives the negated, or complementary, version of the input signal, designated by Vin.
The level shifter circuit 1 further comprises: a first protection transistor 4, of an HV NMOS type (for example, having a second thickness of the gate oxide, greater than the aforesaid first thickness, such as not to cause failure for high voltage values), connected between the first transfer node N1 and a first output terminal OUT1, and having the gate terminal connected to the first input terminal IN1; and a second protection transistor 5, which is also of an HV NMOS type, connected between the second transfer node N2 and a second output terminal OUT2, and having the gate terminal connected to the second input terminal IN2.
The level shifter circuit 1 further comprises: a first output transistor 6, of an HV PMOS type, connected between the first output terminal Out1 and a supply terminal that receives a supply voltage, of a value equal to the high voltage VHV, and having the gate terminal connected to the second output terminal OUT2; and a second output transistor 7, which is also of an HV PMOS type, connected between the second output terminal OUT2 and the supply terminal, and having the gate terminal connected to the first output terminal OUT1.
Operation of the level shifter circuit 1 is now described (it should be noted that, for the purposes of its operation, the distinction between the conduction terminals, i.e., the drain and source terminals, of the various NMOS or PMOS transistors is not relevant).
The input signal Vin, at low voltage, has logic values ‘0’ (low) or ‘1’ (high), being alternatively equal to 0 or to the logic supply voltage Vdd.
The level shifter circuit 1 is configured to supply, on the second output terminal OUT2 the output signal Vout, shifted upwards with respect to the input signal Vin, being alternatively equal to 0 or to the high voltage VHV. The level shifter circuit 1 further supplies, on the first output terminal OUT1 the negated, or complementary, version of the output signal, Vout, having a high value (equal to the high voltage VHV) when the output signal Vout has a low value, and a low value when the output signal Vout has a high value.
During operation, when the input signal Vin is high, the first input transistor 2 and the first protection transistor 4 are both on, whereas the second input transistor 3 and the second protection transistor 5 are both off.
Consequently, the first output terminal OUT1 goes to ground gnd, thus switching-on the second output transistor 7, and the second output terminal OUT2 goes to the high-voltage value VHV, thus switching-off the first output transistor 6. Consequently, the output signal Vout has a high value VHV, shifted to high voltage with respect to the high logic value (Vdd) of the input signal Vin.
The behaviour of the level shifter circuit 1 is similar, when the input signal Vin has a low logic value, supplying at the output a low output signal Vout and the complementary signal Vout with a high value VHV.
The desired level-shifting effect is thus obtained, with the input signal Vin, received on the first input terminal IN1, that switches between gnd and Vdd, and the output signal Vout, supplied on the second output terminal Out2, shifted upwards, which switches accordingly between gnd and VHV.
It should be noted that the first and second protection transistors 4, 5 in the level shifter circuit 1 have the function of protecting the input LV transistors 2, 3 from the high voltage present alternatively on the first output terminal OUT1, or on the second output terminal OUT2.
As illustrated in FIG. 2, a known further embodiment of level shifter circuit, once again designated by 1, envisages, as compared to the circuit of FIG. 1, the presence of a further pair of protection transistors: a third protection transistor 8, of an LV NMOS type, connected between the first input transistor 2 and the first protection transistor 4, and a fourth protection transistor 9, which is also of an LV NMOS type, connected between the second input transistor 3 and the second protection transistor 5.
In this embodiment, the third and fourth protection transistors 8, 9 receive on their respective gate terminal the logic supply voltage Vdd, whereas the first and second protection transistors 4, 5 receive on their respective gate terminal a protection voltage Vp, of an intermediate value between the logic supply voltage Vdd and the high voltage VHV, equal, for example, to 1.8 V in the case where the aforesaid logic supply voltage Vdd is equal to 1 V and the aforesaid high voltage VHV is equal to 3.6 V.
In a way that will be evident, general operation of the level shifter circuit 1 does not differ substantially from what has been illustrated previously with reference to FIG. 1, with the advantage of providing a further level of protection for the LV transistors present in the circuit (thus further reducing the risk of corresponding failure).
Although enabling in general the desired level-shifting operation, according to the modalities described previously, the level shifter circuit 1 is not altogether satisfactory.
In particular, the voltage range in which the level shifter circuit 1 operates in a correct and reliable way is limited, in so far as: if it is desired that the high-voltage value VHV increases above a certain value, the circuit may not be reliable, on account of the voltage limits that may be withstood by the MOS transistors used; if, instead, it is desired for the high-voltage value VHV to drop below a given value, the level-switching function may be jeopardized.
Thus, the level shifter circuit 1 does not offer an adequate flexibility as regards the voltage ranges that may be applied.
Furthermore, the circuit configuration described may not be optimized as regards occupation of area in an integrated embodiment.